1. Field of the Invention
The present invention relates to a semiconductor device that can easily assemble semiconductor elements having pads arrayed along two facing sides of the major surface in a package having electrodes arrayed along all the outer circumferential sides of the major surface of a substrate whereon the semiconductor elements are placed.
2. Background Art
In a conventional semiconductor device having a stacked MCM structure, a dummy wiring is formed on an upper semiconductor element, and the electrical signals from a lower semiconductor element are communicated through the dummy wiring to a lead, which is a terminal for external connection. Thereby, the electrical signals from a lower semiconductor element can be guided by the upper semiconductor element (refer to e.g., Japanese Patent Laid-Open No. 11-220091 (pp. 1-4, FIGS. 1-6)).
For the purpose of the reduction of the area of a semiconductor element due to the optimization of a pad arrangement, and to the simultaneous measurement of a large number of semiconductor elements in wafer test, a semiconductor element having pads arrayed along two facing sides of the major surface has recently been manufactured. Other than a semiconductor element designed to have pads on two sides of the major surface from the beginning, a semiconductor element initially designed and manufactured to array pads along four sides of the major surface and assembled on a QFP has been developed, and the design has been changed so as to array pads along two facing sides of the major surface for realizing the reduction of the area of a semiconductor element and the simultaneous measurement of a large number of semiconductor elements in wafer test. Since such a semiconductor element has already been shipped as a QFP and used in a circuit board, it must be assembled in a QFP for maintaining interchangeability with conventional products even if the pad arrangement of semiconductor elements have been changed.
However, although a conventional semiconductor device may not require an expensive multi-layer substrate for assembling by making the upper semiconductor element guide the electrical signals from the lower semiconductor element, an optimal pad layout or wiring method of easily assembling semiconductor elements having pads on two facing sides, whose demand has been increased, in packages having electrodes on four outer circumferential sides, such as QFP, cannot be known from this technique.